The speed of an application running on a computer, executed by one or more processors, is primarily determined by access speed to information that is to be processed and by the speed with which processed information can be stored until needed either for further processing or for inputting.
Different memory types with different properties, especially different speeds, thereby having different prices, are used in computer systems. Further, different buses used between the memory and a processor running the application, and components connected to the bus affect to the reading and/or writing speed. Further, the characteristics of memories are evolving and a memory used in the computer or by the computer may be updated to a faster one. A basic division between memories is that memory is either a cache which is a buffer memory used as a high speed storage for frequently accessed instructions and data, or the memory is a so called main memory or storage. Basically there are two types of memory I/O (i.e. writing/reading) operations: accessing directly the storage or using the cache through which all data streams pass to and/or from the main memory. Currently using the cache is a default solution. However, sometimes accessing directly the storage may be more efficient and have less overhead.
WO 2008/004149 discloses a solution in which part of a flash memory, which is used as a storage, is allocated to be used as a buffer for the rest of the flash memory in order to minimize a time overhead and wear-out of flash memories. In the solution, all write and read requests pass a memory controller. When the memory controller receives a data stream to be written to the memory, it compares the size of the received data stream to a predetermined number of data packets, and if the data stream is bigger than the predetermined number of data packets, it is directly stored to its target destination, otherwise it is stored for the buffer portion to be stored later to the target destination and to be read from the buffer portion as long as it is there. When data from the buffer portion is stored and there is more than one piece of data having the same target destination, only the newest one is stored.
The solution in WO 2008/004149 still happens within the storage, and the data stream to and from the memory controller passes via a cache, although accessing directly the flash memory might be more efficient.